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Applies to: Cortex-M3
No. This is an optional feature of the ETM architecture and is not included in the Cortex-M3 implementation because the Cortex-M3 is targeted at minimal gatecount and pincount for optimal cost. Also, because the Cortex-M3 has a simple pipeline and no out-of-order execution of opcodes, cycle-accurate trace is deemed to be of less value for this core than for cores which contain more complex pipelines and instruction execution order.
Data tracing is also not supported in the Cortex-M3 ETM for similar reasons, though reduced data trace functionality can be provided via the Data Watchpoint and Trace (DWT) and Instrumentation Trace Macrocell (ITM) units. The DWT contains up to four comparators which can each trace data accesses to an address or range of up to 32kB addresses. The ITM can trace "interesting values" via explicit store instructions in the program code, for example storing an interesting variable or register value to one of up to 32 ITM channels.
The various ETM features which are supported or not supported in Cortex-M3 ETM can be seen by comparing the features described in the fully-featured ETM Control Register described in the Embedded Trace Macrocell Architecture Specification with the implementation-specific description of which Control Register bits are available or tied off in the ETM chapter of the Cortex-M3 Technical Reference Manual.
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