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Applies to: Cortex-M3
TRACECLKIN can come from anywhere outside of the Cortex-M3, either on-chip or off-chip via a pin. Logic in the Trace Port Interface Unit (TPIU) is clocked on the rising edge of TRACECLKIN.
For synchronous (parallel) trace port mode (ports TRACECLK + TRACEDATA):
TRACECLK is TRACECLKIN / 2, divided in the TPIU to clock trace data at the trace capture unit. The output TRACECLK should be delayed on-chip so that the edges of TRACECLK are aligned to the middle of the data period of the trace data.
The trace port clock domain is designed to be entirely asynchronous to all other clock domains in the chip, so it is not restricted by the processor clock speed.
The main restrictions for determining the speed of TRACECLKIN would be:
- data integrity of TRACECLK and TRACEDATA pins (how fast can the chip's output buffers drive the impedances of the off-chip connections, and how accurately can the dual edges of TRACECLK be maintained within the data eye of TRACEDATA?)
- capability of the trace port analyzer (TPA) - does your TPA specify a maximum frequency for trace?
For Serial Wire Output (SWO) / Serial Wire Viewer (SWV) mode:
Because the programmable divide ratio has a large range, TRACECLKIN speed is not very important except in so far as it needs to be high enough to give the full baud rate that your trace connection intends to support.
Assuming that the baud rate on a serial trace connection is likely to be lower than the processor clock speed, the simplest solution will be to source TRACECLKIN from the same clock source as the processor's FCLK/HCLK clocks - although the design of the TPIU is intended to support any asynchronous clock source for TRACECLKIN(*).
(*) - Early versions of Cortex-M3 (r0 and r1) TPIU have some restrictions on this.
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