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At what point in an AXI bus transfer is davalid asserted?

Applies to: PL330 AXI DMA Controller


In Figures 2-9 (page 2-20) and Figure 2-10 of the PL330 TRM (r0p0), the davalid occurs 1-cycle after the data burst, 
so does the end of the data burst in the figures correspond to AXI BRESP?


In figures 2-9 - 2-11 in the TRM, the Data Burst on the "DMA activity on
the AXI data bus" represents the complete data transfer, including the
BRESP (or the final RRESP in the case of a read transfer), i.e. it
corresponds to the AXI BRESP being asserted in the figures, as you
correctly assumed.

The PL330 sees the returning BRESP; it then acknowledges it by removing
the write from the store queue and attempting to assert davalid. davalid
is, therefore, asserted one cycle after the BRESP is seen by the PL330.

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