ARM Technical Support Knowledge Articles

What are the AHB bus transactions that PL080 can achieve?

Applies to: PL08x DMAC (DM & SM)


Because of the PL080's small FIFO depth of 4 words, the longest burst
you can achieve from the device is an INCR4 burst, IF you are
transferring word (32-bit) quantities. It is possible to achieve INCR8
bursts if transferring half-words and INCR16 bursts if transferring byte
quantities, i.e. 

burst size	= (FIFO depth x 4)/width of transfer in bytes
		= (4 x 4)/4 = 4 words, or
		= (4 x 4)/2 = 8 half words, or
		= (4 x 4)/1 = 16 bytes.

Now, whether INCR4 (say) bursts are achievable in practise depends on a
number of factors, such as whether you are using both masters in the
PL080, the number of wait states in the memory, arbitration etc. It is
arguably more efficient to use a single master for both source and
destination transfers since the PL080 will be forced to allow the FIFO
to fill (a defined length burst cannot be broken) before starting the
write, which, subject to arbitration, will be allowed to complete. If
both source and destination transfers are word-size then you should see
INCR4 bursts on both sides of the FIFO (or INCR8/16 if using

If using both masters, then a 'streaming' effect happens whereby the
FIFO will fill initially with an INCR4 (8/16); as soon as this has
happened, the destination side starts to transfer one or two data items.
Consequently, as soon as there is a free slot or two in the FIFO, the
source side will fill them, with the result that after the initial INCR4
to fill the FIFO, the rest of the transfers tend to be INCRs of length
one or two.

If you are transferring 'large' bursts of (word) data, they will be
broken down into INCR4 bursts where possible (subject to the above
restrictions) and INCRs for the rest.

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