|ARM Technical Support Knowledge Articles|
Applies to: Debug and Trace
No, ETMs are designed to operate at the processor clock speed in any given technology (although in any ASIC technology the addition of extra gates can potentially have an effect upon the overall performance of the SoC).
ETMs capture the processor behavior at processor clock speed. In most cases, the ETM has an asynchronous boundary (a FIFO) so that the trace information can be drained at an asynchronous (lower) frequency. Trace data is not normally exported off-chip at the same clock speed as the processor is running.
The processor and ETM may offer a use mode where the processor can be stalled if the ETM's FIFO becomes full. The mode prevents the loss of trace data during bursts of high trace bandwidth requirement, at the cost of altering the processor behavior. In this mode, the ETM could affect processor performance by causing stall cycles.
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