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Applies to: ARM1176
First calculate the number of cycles required to do a single write to all memory addresses.
This depends on the memory sizes (maximum sizes are assumed here).
For multiple instance memories, the total addresses is divided by 2 because
the RAM width is <= 32 bit and the MBIST controller data width is 64 bit which enables
2 RAM blocks to be tested simultaneously.
ITCM = 16K / 2 (2 * 8kx32)
I$ data = 16K / 2 (8 * 2kx32)
I$ tag = 2K / 2 (4 * 512x23)
DTCM = 16K / 2 (2 * 8kx32)
D$ tag = 2K / 2 (4 * 512x25)
D$ data = 16K / 2 (8 * 2kx32)
D$ dirty = 512
TLB = 64
BTAC = 128
Total cycles = 35520
Depending on the MBIST algorithm selected, the test length will be a multiple of this figure.
For example, March C+ algorithm is 14N in length, so we multiply the RAM size by 14 = 497280 cycles.
In addition, there are a few setup cycles (approx. 80) at the start of each RAM test.
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