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USB OTG support on PB11MPCore, PB1176JZF-S and PB-A8

Applies to: Versatile Baseboards



The PB11MPCore, PB1176JZF-S and PB-A8 baseboards employ the same circuit design for the user USB ports. This is based on the NXP ISP1761 USB chipset, which has three USB ports available to the programmer. The ARM baseboard design uses ports 2 and 3 as host ports, and these are connected to the A-type USB sockets on the development board. Port 1 on the ISP1761 is connected to the 'mini AB' type USB socket on the board, labelled 'USB OTG'. The design intent was that this port could be used in either host or peripheral modes.


Elements of the current PCB design on all three board types mean that Port 1 does not fully comply with the USB OTG specification and hence may not work as expected in all scenarios. Details of the non-compliance and possible workarounds are described here. The relevant part of the PB11MPCore schematic is included here to aid understanding of the problem. The USB port design on the other boards listed above is almost identical. Click on the thumbnail to download a larger image:

PB11MPCore User USB ports schematic thumbnail.png

1. VBUS switching

When a USB port behaves as a host, it provides a current-limited 5V power supply output on its VBUS pin. When acting as a peripheral, a USB device receives 5V on the VBUS pin, which may or may not be used to power the device. Port mode is indicated fundamentally by the 'ID' pin on the attached USB cable. USB type mini A connectors should have their ID pin grounded, which tells the USB port hardware to behave as a host.

The ARM baseboard USB circuit design incorporates LM3525 USB switch ICs, which provides the ability to switch the VBUS outputs on/off under software control. This can only be done for all three USB ports simultaneously. The LM3525 also provides the over-current detection, should an attached USB peripheral draw too much power from VBUS.

The existing circuit design does not however automatically shut off the VBUS 5V output when a USB mini B type connector is plugged in to the OTG port, as would be the case if the development board were being used to emulate a USB peripheral.

This switching should be done by board hardware monitoring the state of the ID pin on the mini USB connector. NXP's AN10053 gives an example FET switch circuit that does this, but this circuit is not implemented on the board, nor could it be retro-fitted. It is incompatible with the existing overcurrent detection switches (LM3525) which force use of the 'digital' overcurrent detection scheme on the ISP1761. All three ports must use the same overcurrent detection mode, according to the NXP datasheet.

2. VBUS capacitance

The OTG supplement to the USB 2.0 specification requires different decoupling capacitances on the VBUS line depending on whether the device is a host or peripheral: 1.0uF < CVBUS < 6.5uF for a peripheral device and CVBUS > 96uF for a host device. The FET switch circuit in AN10053 takes care of this, but this circuit is not implemented on the ARM boards. In our design the VBUS line has zero intentional capacitance when the LM3525 output is switched OFF and 100nF in parallel with 10uF when switched on. This discrepancy may or may not cause a problem in your development system setup.

3. Series termination resistors

There are two 33R series termination resistors in each port's USB data lines between the ISP1761 and the USB socket. These resistors are not mandated by the NXP datasheet and as such they may or may not be detrimental to signal quality.


Possible workarounds exist for this problem, but their viability depends on exactly what your application demands from the three USB ports and to what extent you wish to have automatic switching between peripheral and host modes on Port 1.

Workaround for issue 1(a)

The easiest way to prevent the PB11MPCore from supplying 5V from the USB 'A-type' plug back to the host would be to disconnect the VBUS line somewhere. This could be achieved by simply cutting the wire in the USB A-mini B cable, or one could modify the internal gray cable in the PB11MPCore chassis that connects J48 on the motherboard to J1 on the 'Front panel IO board' (HBI-0175). This would have the same effect but involves modifying (and voiding the warranty) on the entire development board rather than just destroying a cheap USB cable.

If you put the break in the USB cable from the external host, this would mean that disconnecting the external host, swapping the USB A-miniB cable for a miniA-B cable and reconnecting to an external peripheral would solve the power switching problem. This is because the PB11MPCore doesn't need to receive 5V on the OTG socket when acting as a peripheral, whereas it can supply it from that socket to an external peripheral when acting as a host.

Workaround for issue 1(b)

Since the Port power is not enabled until software writes to the correct register(s), one could theoretically enable/disable VBUS under software control. Usting this method, it is only possible to enable/disable all three ports at once so this may be of no use in your development scenario.

Workaround 2

There is no practical workaround for this issue.

Workaround 3

If these resistors are found to cause signal degradation, they could either be shorted out with wire links or removed and replaced with zero-Ohm resistor links.

Long term solution:

We have no current plans to rectify these anomalies with a new revision of the PCBs, due to the high cost of redesigning several different boards in relation to the low number of users affected.


User USB ports schematic.png
User USB ports schematic_thumb.png

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