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Hold at reset example

Applies to: Fast Models

Answer

Introduction

The asHoldAtReset component illustrates how a component can drive a port at the beginning of simulation. In both example systems provided , the output ports of the component are connected to the reset port(s) of the core.

Parameters

Name Type Default Description
Hold core0 in reset bool FALSE if TRUE reset[0] signal will be driven at simulation reset
Hold core1 in reset bool FALSE if TRUE reset[1] signal will be driven at simulation reset
Hold core2 in reset bool FALSE if TRUE reset[1] signal will be driven at simulation reset
Hold core3 in reset bool FALSE if TRUE reset[1] signal will be driven at simulation reset

Ports

Name
Protocol Master/Slave Description
clk_in ClockSignal Slave Input clock port, should be connected to the master clock
reset_out Signal Master 4 element signal port, should be connected to the collapsed reset port on a MP core compoent

How does it work?

This component uses a ClockTimer component and is configured, in the init behaviour, to recieve a single callback at the begining of the simulation (time = 0). During this callback the component checks its parameter, if TRUE and the corresponding reset port is connected, it sets the signal. The component does not clear any of the reset signals

Attachments

asHoldAtReset.zip

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