ARM Technical Support Knowledge Articles

Which architectures support the WFI instruction?

Applies to: ARM Architecture and Instruction Sets, Processor Cores, RealView Development Suite (RVDS)

Answer

The WFI instruction is defined as a 'hint' to the processor that there is no work that needs to be done at the current time.  Depending upon the processor, this may mean entering 'wait for interrupt' mode, where the processor clock is stopped until an interrupt or debug event occurs.

ARMv5 (for example the ARM926EJ-S) does not include the WFI instruction.  However, most ARMv5 processors implement a "wait for interrupt" mode that is entered by a write to coprocessor 15:

MCR p15, 0, Rn, c7, c0, 4

This is implemented by the the ARM926EJ-S, ARM966E-S, ARM968E-S and ARM946E-S.

ARMv6 (with no extensions) does not implement the WFI instruction.  The only ARM processor implementing ARMv6 is ARM1136J-S rev 0.  This processor implements "wait for interrupt" mode with a CP15 write as in ARMv5.  On ARMv5 and ARMv6 processors, attempting to execute the WFI instruction will cause a undefined instruction exception to be taken.

ARMv6K and ARMv6T2 include the WFI instruction, meaning that these processors do not cause an undefined instruction exception when the WFI instruction is executed.  However, the ARM1136J(F)-S rev 1 and ARM1176JZ(F)-S (architecture ARMv6K), as well as the ARM1156T2(F)-S (architecture ARMv6T2) treat the WFI as a NOP, and implement the CP15 method for entering "wait for interrupt" mode. 

ARM11MPCore (architecture ARMv6K) supports both the WFI instruction or the CP15 method to enter "wait for interrupt" mode.

ARMv7 processors (including Cortex-A8, Cortex-A9, Cortex-R4 and Cortex-M3) all implement the WFI instruction to enter "wait for interrupt" mode.  On these processors, the coprocessor write used on earlier processors will always execute as a NOP.  It is therefore possible to write code that will work across ARMv6K, ARMv6T2 and all profiles of ARMv7 by executing both the MCR and WFI instruction, though on ARM11MPCore this will cause "wait for interrupt" mode to be entered twice.  To write fully portable code that enters "wait for interrupt" mode, the CPUID register must be read at runtime to determine whether "wait for interrupt" is available and the instruction needed to enter it.

ARM RealView Compilation Tools allow the WFI instruction to be generated for all architectures that support the WFI instruction, including those which execute it as a NOP.  This applies to using the WFI instruction with the assembler, and the __wfi() intrinsic (available in RVCT 3.1 and later) with the compiler.

In the assembler, the correct instruction to enter "wait for interrupt" can be selected using the built in variable {ARCHITECTURE} or {CPU}, for example:

IF ({ARCHITECTURE} = "6"):LOR:({ARCHITECTURE} = "6K"):LOR:({ARCHITECTURE} = "6T2"):LOR:({ARCHITECTURE} = "6Z")
MOV R0, #0
MCR p15, 0, r0, c7, c0, 4
ELIF ({ARCHITECTURE} = "5T"):LOR:({ARCHITECTURE} = "5TE"):LOR:({ARCHITECTURE} = "5TEJ")
MOV R0, #0
MCR p15, 0, r0, c7, c0, 4
ELIF ({ARCHITECTURE} = "7"):LOR:({ARCHITECTURE} = "7-A"):LOR:({ARCHITECTURE} = "7-R"):LOR:({ARCHITECTURE} = "7-M")
WFI
ELSE
NOP
ENDIF

Note:  This code generates a NOP for ARMv4 processors, even though some of them (such as the ARM920T) do support a "wait for interrupt" mode.  It could be extended to distiguish the ARMv4 cores that do support "wait for interrupt" using the {CPU} variable.

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