ARM Technical Support Knowledge Articles

How do I change the CPU and bus frequency on PB-A8?

Applies to: PB-A8

Scenario

The default CPU clock speed on the PB-A8 system is 750MHz and the test chip internal AXI runs at 62.5MHz. Sometimes it is necessary to change the clock speeds or ratio for test purposes, or to make more optimal use of the trace port (see FAQ: Why is trace bandwidth so limited on PB-A8?).

Please note that the factory default frequencies were carefully chosen to give the highest performance with a stable system. It is therefore unlikely that changing the clock settings and relationships will produce greater system performance.

Answer

The following diagram shows how registers in the PB-A8 "Southbridge" FPGA control the test chip reference clock and PLL/divider settings:

PB-A8 test chip clock architecture

[Click on thumbnail to download full-size diagram]

To make a change to the base reference clock or test chip PLL/divider settings, it is necessary to write the new value into the memory-mapped register specified below and then perform a soft reset of the system. The reset is necessary to trigger the clock settings update and also to allow all the PLLs and DCMs in the system to attain lock before the CPU and AMBA infrastructure start running. The system should come back up with the new clock settings in effect. The following sequence should be followed:

  1. Write value 0xA05F to the SYS_LOCK register @ 0x10000020. This unlocks the clock control registers for modification
  2. If required, write the new ICS307 control value to the SYS_OSCRESET5 regsister @ 0x100000DC
  3. If required, write the new test chip PLL/divider settings to the SYS_PLL_RESET register @ 0x10000100
  4. Generate a soft reset by pushing the reset button on the PB-A8 front panel, or by issuing the reset command in the RVD Cmd window
  5. The new REFCLK and PLL control values should appear in SYS_OSC5 @ 0x100000D4 and SYS_PLL_INIT @ 0x1000007C
  6. Run your test code and verify that the system is stable with the new settings

Note that it is possible to change these settings by writing the new values to the SYS_OSC5 and SYS_PLL_INIT registers. This is not the recommended method however, since this will cause the changes to occur immediately, which will usually lock up the system and require a hard reset to recover.

The following table lists some common register settings for different CPU:AXI clock ratios. It is not a definitive list of all possible working combinations. Some experimentation will be required on the part of the user to determine all of the usable combinations which keep every component of the clock generation and distribution circuits within limits. For example, the VCO in the test chip PLL can only output frequencies in the range ~200MHz to ~2GHz.

Example register settings for PB-A8 CPU clock ratios
0 (default) 1 2 3 4
REFCLK 50MHz 50MHz 50MHz 50MHz 50MHz
SYS_PLL_* 0x0B0101D0 0x040501D0 0x02090270 0x03090270 0x010E01D0
ADIV 0x0B (11) 0x04 0x02 0x03 0x01
ODIV 0x01 0x05 0x09 0x0E   (14) 0x0E (14)
FBDIV 0x01D (29) 0x01D (29) 0x027 (39) 0x027 (39) 0x1D (29)
REFDIV 0x0 0x0 0x0 0x0 0x0
CPU CLK 750MHz 250MHz 200MHz 200MHz 100MHz
AXI CLK 62.5MHz 50MHz 66.67MHz 50MHz 50MHz
C. Dhry/s 2.5M 0.9M 0.7M 0.7M 0.35M

Table notes:

The CPU and AXI clock frequencies can be calculated from the data above with the following formulae. Note that the calculations assume the PLL is not bypassed (BYPASS = 0). The default figures for CPU CLK are shown as an example:

PB-A8 test chip clock equations

To help test the above settings, a set of Boot Monitor configuration scripts is attached to this Knowledge Article. This will allow the user to quickly program one of the above sets of parameters without the need to write any code or manually poke the values into the registers via a debugger as per the numbered list above. Please follow these steps:

1. Uncompress the script files and copy them to the root directory of an SD or CF card
2. Insert this flash memory card into the appropriate slot on the PB-A8
3. Connect a serial terminal to the PB-A8 on the UART0 port
4. Power on the PB-A8
5. At the "DOS" prompt on the terminal, run one of the C* scripts from the flash memory card by entering (for example): @C1
6. The system should write to the registers listed above and reboot itself. If it does not, press the "Soft Reset" button on the front panel
7. After the system has rebooted, run the "D" script and see whether the clock settings have taken effect (look at the SYS_PLL_INIT register @ 0x1000007C)
8. Start debug/trace session with the new clock settings in effect.

Attachments

clock_equations.gif
PB-A8_clock_set_scripts.zip
PB-A8_test_chip_clock_architecture.gif
PB-A8_test_chip_clock_architecturethumb.gif

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