|ARM Technical Support Knowledge Articles|
Applies to: PB-A8
The default CPU clock speed on the PB-A8 system is 750MHz and the test chip internal AXI runs at 62.5MHz. Sometimes it is necessary to change the clock speeds or ratio for test purposes, or to make more optimal use of the trace port (see FAQ: Why is trace bandwidth so limited on PB-A8?).
Please note that the factory default frequencies were carefully chosen to give the highest performance with a stable system. It is therefore unlikely that changing the clock settings and relationships will produce greater system performance.
The following diagram shows how registers in the PB-A8 "Southbridge" FPGA control the test chip reference clock and PLL/divider settings:
[Click on thumbnail to download full-size diagram]
To make a change to the base reference clock or test chip PLL/divider settings, it is necessary to write the new value into the memory-mapped register specified below and then perform a soft reset of the system. The reset is necessary to trigger the clock settings update and also to allow all the PLLs and DCMs in the system to attain lock before the CPU and AMBA infrastructure start running. The system should come back up with the new clock settings in effect. The following sequence should be followed:
Note that it is possible to change these settings by writing the new values to the SYS_OSC5 and SYS_PLL_INIT registers. This is not the recommended method however, since this will cause the changes to occur immediately, which will usually lock up the system and require a hard reset to recover.
The following table lists some common register settings for different CPU:AXI clock ratios. It is not a definitive list of all possible working combinations. Some experimentation will be required on the part of the user to determine all of the usable combinations which keep every component of the clock generation and distribution circuits within limits. For example, the VCO in the test chip PLL can only output frequencies in the range ~200MHz to ~2GHz.
|ODIV||0x01||0x05||0x09||0x0E (14)||0x0E (14)|
|FBDIV||0x01D (29)||0x01D (29)||0x027 (39)||0x027 (39)||0x1D (29)|
The CPU and AXI clock frequencies can be calculated from the data above with the following formulae. Note that the calculations assume the PLL is not bypassed (BYPASS = 0). The default figures for CPU CLK are shown as an example:
To help test the above settings, a set of Boot Monitor configuration scripts is attached to this Knowledge Article. This will allow the user to quickly program one of the above sets of parameters without the need to write any code or manually poke the values into the registers via a debugger as per the numbered list above. Please follow these steps:
1. Uncompress the script files and copy them to the root directory of an SD or CF card
2. Insert this flash memory card into the appropriate slot on the PB-A8
3. Connect a serial terminal to the PB-A8 on the UART0 port
4. Power on the PB-A8
5. At the "DOS" prompt on the terminal, run one of the C* scripts from the flash memory card by entering (for example): @C1
6. The system should write to the registers listed above and reboot itself. If it does not, press the "Soft Reset" button on the front panel
7. After the system has rebooted, run the "D" script and see whether the clock settings have taken effect (look at the SYS_PLL_INIT register @ 0x1000007C)
8. Start debug/trace session with the new clock settings in effect.
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