ARM Technical Support Knowledge Articles

How does the PL340 generate memory address from the AXI address?

Applies to: PL340 AXI SDRAM Controller

Answer

PL340 generates memory addresses in the following manner:

1) When the addressing mode is selected as BRC in the memory configuration register:

    Bank address = AXI address[row_bits + column_bits + shift + 1 : row_bits + column_bits + shift]

    Row address = AXI address[row_bits + column_bits + shift - 1 : column_bits + shift]

    Column address = AXI address[column_bits + shift - 1 : shift]


2) When the addressing mode is selected as RBC in the memory configuration register:

    Row address = AXI address[row_bits + column_bits + shift + 1 : column_bits + shift + 2]

    Bank address = AXI address[column_bits + shift + 1 : column_bits + shift]

    Column address = AXI address[column_bits + shift - 1 : shift]

where

    row_bits and column_bits are the values programmed in the mem_cfg register

and

     shift = memory width in bytes - 1

Row address is issued on the add[15:0] bus on the PL340 memory interface during the ACTIVATE command. Column address is issued on the add[15:0] bus during the READ/WRITE command. Bank address is issued on ba[1:0] during the ACTIVE, READ, WRITE or PRECHARGE commands.

Article last edited on: 2009-07-27 10:05:10

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