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What is the correct JTAG IDCODE for my Cortex processor?

Applies to: Cortex processors

Answer

The Cortex families of processors are designed to comply with ARM's CoreSight debug infrastructure, and therefore do not contain individual TAPs; instead, they have a debug connection which complies to the CoreSight Debug Access Port (DAP) requirements. A DAP consists of a Debug Port (DP) for external pin protocol (eg. JTAG or Serial Wire), one or more Access Ports (AP) communicating with debuggable components inside the SoC, and a DAP bus linking the DP to one or more APs).

The SWJ-DP is a single JTAG-capable TAP controlling one or several debug subsystems on the SoC. If an SoC provides a JTAG debug interface and contains any CoreSight debug components (including any Cortex processor) you should expect to see the standard JTAG IDCODE of a single CoreSight SWJ-DP as one TAP on the JTAG chain.

The CoreSight protocol indicates that when a debugger identifies the debug connection as a CoreSight DP, it should then interrogate the debug bus to identify which Access Ports (such as the Cortex-M3's AHB Access Port - AHB-AP, or a general Debug APB Access Port - APB-AP) are present, and should interrogate each AP's ROM Table to identify that debug subsystem's unique Peripheral ID code, and potentially then go on to identify the individual components contained in that subsystem, such as the Cortex core itself.

The IDCODE tells you that you have connected to a particular revision of an SWJ-DP CoreSight Debug Port component, nothing more. You can not infer anything about what CoreSight debug infrastructure is behind this DP simply from the IDCODE.

There is no requirement that a particular Cortex processor is implemented together with any specific version of DP. Identifying the TAP as a CoreSight DP should trigger the debugger to commence the target identification procedure of reading the Debug ROM Table, attempting to match the unique combination of Peripheral IDs with any known device, and if no match is found, interrogating each component referenced in any of the Debug ROM Tables.

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