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Applies to: ARM1176
The longest possible burst on the AXI data bus is 7, caused by a non-cacheable LDM of 7 or more registers aligned to an appropriate boundary, or STM of 7 or more registers (cache miss, non-cacheable or write-through).
Where the core needs to read or write 8 words, it would instead do a read of 4 double words. Accesses of more than 8 words (e.g a LDM or STM of 9 or more registers) are broken on a cache line boundary so, a burst which reads 8 words is the longest possible, but will be performed as a burst of length 4 and size 64-bits.
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