|ARM Technical Support Knowledge Articles|
Applies to: Cortex-M3
The C_DEBUGEN bit in the NVIC Debug Halting Control and Status Register (DHCSR) can only be programmed via the DAP, so you cannot halt the core without a debugger. Therefore, you will need to have some sort of debug simulation model to halt the core.
Once the C_DEBUGEN bit is set, the core can be halted by setting the C_HALT bit in the DHCSR, this bit can either be written by the debugger or by the software running on the core.
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