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What are the differences in the way the ARM VICs handle vectored and non-vectored interrupts?

Applies to: PL192 Vectored Interrupt Controller

Answer

A Vectored Interrupt Controller will provide the address of the handler in a register; the ARM PrimeCell PL192 provides this address in the VICADDRESS register, located at 0xF00 from the controller's base address. By locating the VIC at the recommended address of 0xFFFFF000 and programming address 0x18, i.e. the IRQ vector address in the vector table, with

   LDR PC, [PC, #-0x120]

the core will read the address of the currently-active interrupt's handler directly from the VICADDRESS register.

To handle non-vectored interrupts, the core must be programmed at address 0x18 with a branch to an interrupt dispatcher so that it can interrogate the interrupt controller to work out which interrupt had gone off.

There are examples of both types of handler available in the PL192 and PL190 Technical Reference Manuals, available from http://infocenter/help/topic/com.arm.doc.ddi0273a/CACIGBJG.html and http://infocenter/help/topic/com.arm.doc.ddi0181e/Babgahcd.html respectively. Please note that in PL190, the location of the Vector Address Register differs from its location in PL192 - hence the slight difference in the example code.

In the case of the FIQ, neither PL192 nor PL190 treat it as a vectored interrupt. Conventionally, the FIQ handler is placed directly at address 0x1c, removing the need to branch to a handler first. It can, of course, be handled in this way if required.

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