|ARM Technical Support Knowledge Articles|
Applies to: Cortex-M3
If an interrupt occurs, but cannot currently be handled by the core because, say, a higher priority interrupt is currently being handled, the new interrupt is set to PENDING by hardware. The SETPEND registers allow software to both read the current PENDING status of all the interrupts and to force an interrupt to the PENDING state. This is the equivalent of software generating an interrupt that cannot currently be handled.
Similarly, the CLRPEND registers can be read by software to determine the PENDING state of the interrupts and written to clear a PENDING interrupt.
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