|ARM Technical Support Knowledge Articles|
Applies to: ARM946E-S
The ARM946E-S will generate INCR (unspecified length) bursts whenever a STM (Store Multiple), STRD (Store Double word), an uncached LDM (Load Multiple) or a LDRD (Load Double word) instruction is executed. The only other occasion where the ARM946E-S will generate INCR bursts is if the core was degranted the bus part way through a cache line fill or cache line write back. When the core comes back onto the bus it would complete the operation as INCR accesses.
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