ARM Technical Support Knowledge Articles

How can I generate LOCKed, Exclusive and burst transfers on ARM926 and ARM1176 cores?

Applies to: ARM1176, ARM926EJ-S


Locked accesses:

Locked accesses are generated using the SWP instruction. This is, in fact, the only way to generate a locked access from an ARM926 or ARM1176 core and has to be done from assembler, since the ARM compiler cannot generate this instruction.

The syntax is SWP{<cond>} <Rd>, <Rm>, [<Rn>] and will swap the value in a register with the value at a memory address.

Exclusive accesses:

Exclusive accesses are performed by the LDREX and STREX instructions. The ARM v6 (but not the ARM v6-M), ARM v7-A&R and ARM v7-M Architecture Reference Manuals describe, in detail, the use of LDREX and STREX family of instructions. There are also a number of Knowledge Articles, available from our website and then searching for LDREX under the ARM Technical Support Knowledge Articles section. These instructions are not available on the ARM926EJ-S.


The ARM926EJ-S will not generate undefined-length INCR bursts - it can only generate SINGLEs, INCR4, INCR8 or WRAP8 bursts. See section 6.2
"Supported AHB transfers" in the ARM926EJ-S (r0p4/r0p5) Technical Reference Manual for details on how to generate these bursts.

The ARM1176JZF-S will only generate FIXED (on the DMA port only), INCR and WRAP bursts, of varying lengths. For a full list of burst types and
lengths and how to generate them, see sections 8.4 "Instruction Fetch Interface transfers", 8.5 "Data Read/Write Interface transfers" and 8.6 "Peripheral Interface transfers" in the ARM1176JZF-S TRM.

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