|ARM Technical Support Knowledge Articles|
Applies to: ARM926EJ-S
If the MMU is disabled (M=0 in the CP15 c1 Control Register), all memory is noncacheable and nonbufferable (NCNB).
If the MMU is enabled (M=1) then the use of the write buffer is controlled by the page table descriptor.
If the page table descriptor has C bit=0, then memory is noncacheable and the B bit controls bufferability:
B bit=0 : nonbufferable (NCNB)
B bit=1 : bufferable (NCB)
If the page table descriptor has C bit=1, then all writes are both cacheable and bufferable and the B bit controls cache policy:
B bit=0 : writethrough
B bit=1 : writeback
The Data Cache enable bit C in the CP15 c1 Control Register has no effect on whether the write buffer is used.
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