ARM Technical Support Knowledge Articles

Does Cortex-M3 need Memory Barrier instructions?

Applies to: Cortex-M3


It is recommended to insert a DSB before any WFI to ensure that Erratum 548721 can not cause a problem. If you know that the processor will be Cortex-M3 r2p0 or newer, this is not necessary as the erratum is corrected in r2p0.

In general, Cortex-M3 does not require memory barrier instructions for simple memory accesses as all memory accesses are executed in-order.

Memory accesses which have side-effects such as altering the memory system (eg. memory map changes) should be used with memory barriers to ensure that the change is complete before further memory accesses are initiated.

It is good practice to consider adding memory barrier instructions for any code which makes multiple memory accesses and relies on the processor correctly ordering the transfers; while Cortex-M3 will perform the memory accesses in program order, more complex cores may permit out-of-order completion - so including memory barriers makes code more portable.

It is not necessary to insert memory barriers for Read-After-Write or Write-After-Read to the same address, as processor cores include hazard checking for these cases. If external levels of buffering are included in the SoC, then the designer must take care of these hazards in the external buffering logic.

A detailed explanation of all the cases in which a Barrier might be required is included in Application Note 321:

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