ARM Technical Support Knowledge Articles

How do I change clock settings on the PB11MPCore?

Applies to: PB11MPCore

Answer

Scenario:

On the PB11MPCore the default CPU clock frequency is 210Mhz and the default AXI bus frequency is 70Mhz. These values have been selected to provide the highest performance whilst keeping the system stability, however users often want to change the default clock settings for benchmarking, test purposes, etc.

An inappropriate procedure to change the clock settings can lead to system lock-up problems and as a consequence the need of issuing a hardware reset for system recovery.

In this Knowledge Article we discuss some alternative methods that can be used to change the clock settings safely.

Solution:

The PB11MPCore contains seven programmable clock generators (oscillators) that provide reference frequencies to different clocks on board. Please refer to the PB11MPCore User Guide for a description of the PB11MPCore clocks.

infocenter.arm.com/help/topic/com.arm.doc.dui0351c/DUI0351C_pb11mpcore_user_guide.pdf

Following are the possible methods to control the output values of these clock generators:


Method 1:

The Boot Monitor "Configure" sub-menu has a command that shows the available oscillators on the motherboard and the correspondent reset frequencies. It also has a command that allows for changing the oscillators output frequency.

As an example, below it shows how to change OSCCLK5 which is the reference clock for the CPU from 70Mhz to 60Mhz. The Boot Monitor makes changes to the clock frequency in small increments until the target frequency is reached. This is why the change appears to take effect inmediately and a software reset is not necessary.


ARM PB11MPCore Boot Monitor
Version:    V4.1.7
Build Date: Feb 17 2009
Tile Site : Tile Not Fitted
Endian:     Little
> CONFIGURE
Configure> HELP
DISABLE DATA CACHE   - Disable Data cache
DISABLE I CACHE      - Disable Instruction cache
DISABLE MMU          - Disable mmu
DISPLAY CLOCKS       - Display system clocks
DISPLAY DATE         - DISPLAY DATE
DISPLAY HARDWARE     - Display hardware info
DISPLAY TIME         - DISPLAY TIME
ENABLE DATA CACHE    - Enable Data cache
ENABLE I CACHE       - Enable Instruction cache
ENABLE MMU           - Enable mmu
EXIT                 - Return to Main Menu
HELP                 - List commands
QUIT                 - Alias for 'EXIT'
SET BAUD             - SET BAUD <port> <rate>
SET CLOCK            - Set frequency of clock n
SET DATE             - SET DATE <dd/mm/yy>
SET TIME             - SET TIME <hh:mm:ss>
Configure> DISPLAY CLOCKS
Clocks
======
  Clock 0  frequency = 100.00MHz
  Clock 1  frequency = 40.00MHz
  Clock 2  frequency = 25.00MHz
  Clock 3  frequency = 50.00MHz
  Clock 4  frequency = 25.00MHz
  Clock 5  frequency = 70.00MHz
  Clock 6  frequency = 24.00MHz

Configure> SET CLOCK 5 FREQUENCY 60
ARM PB11MPCore Boot Monitor
Version:    V4.1.7
Build Date: Feb 17 2009
Tile Site : Tile Not Fitted
Endian:     Little
Configure> DISPLAY CLOCKS
Clocks
======
  Clock 0  frequency = 100.00MHz
  Clock 1  frequency = 40.00MHz
  Clock 2  frequency = 25.00MHz
  Clock 3  frequency = 50.00MHz
  Clock 4  frequency = 25.00MHz
  Clock 5  frequency = 60.00MHz
  Clock 6  frequency = 24.00MHz

Method 2:

The "selftest" program provides an option to change the reference clock for the CPU. The selftest image "selftest.axf" is provided with the Versatile Family CD under the following default installation path:

C:\Program Files\ARM\Versatile\PB11MPCore_HBI0159\3.7\1\software\projects\selftest\build\rvds3.0\Debug

A debugger like RVD needs to be used to load and run the selftest program.  Below it shows the RVD console output after loading and running the selftest image and choose the "Clocks" option. Please note that this option only allows for changing the CPU reference clock. Consequently the AXI bus frequency will also be changed as the fixed ratio CPU:AXI is 3. The selftest uses the same "small-steps" algorithm for changing the clock frequency as Method 1. 

RealView/PB11MPCore Test Suite, Version 3.10 Build date: Jan 28 2009
Copyright (C) ARM Ltd 2008. All rights reserved.
FPGA Build: 3
Summary of results
====================================
1 AACI (Audio)            : Not Run
2 MMCI (MultiMedia Card)  : Not Run
3 SCI  (SmartCard)        : Not Run
4 USB OTG and Host ports  : Not Run
5 DMA memory transfer     : Not Run
6 PCI config/mem space    : Not Run
7 SMSC9118 Ethernet       : Not Run
8 CLCD and DVI            : Not Run
9 SSP  (EEPROM)           : Not Run
10 UART0/1/2/3 Interface   : Not Run
11 Character LCD           : Not Run
12 LEDs and Switches       : Not Run
13 GPIO Loopback           : Not Run
14 Keyboard (and Loopback) : Not Run
15 Mouse                   : Not Run
16 SDRAM/SRAM Memory       : Not Run
17 Compact Flash           : Not Run
18 RTC and TOY clock       : Not Run
19 Timer                   : Not Run
20 Clocks                  : Not Run
21 Run Production Tests

Processor clock reference  : 70 MHz
Select the test you wish to run. (X - Exit)
Choice: 20
Testing Clocks                
Current Processor clock reference :  70 MHz
Note: The typical clock limits with the default clock
      divide ratio is 50MHz to 70MHz.
Note: Setting the clock value beyond the board limit
may cause the system to stop responding.
Please enter the new clock reference (50MHz to 70MHz): 60
Reading Clock Test registers...
Clocks                     : test result : PASS


Method 3:

This method requires manual configuration of the oscillators registers. A debugger like RVD needs to be used to set the SYS_OSCRESETx registers in order to vary the frequency of each individual OSCCLKx. The following sequence is an example to change the reference clock for the CPU:

  1. Write value 0xA05F to the SYS_LOCK register @ 0x10000020. This unlocks the clock control registers for modification.
  2. If required, write the new ICS307 control value to the SYS_OSCRESET5 regsister @ 0x100000DC.
  3. Generate a soft reset by pushing the reset button on the PB11MPCore front panel, or by issuing the reset command in the RVD Cmd window.
  4. The new REFCLK value should appear in SYS_OSC5 @ 0x100000D4.
  5. Run your test code and verify that the system is stable with the new settings.

The following table shows some example register configurations for different CPU and AXI bus frequencies.

REFCLK [Mhz]

SYS_OSCRESET5 @0x100000DC CPU [Mhz]  AXI Bus [Mhz] 
35 0x32C3F 105 35
40 0x32C48 120 40
45 0x32C52 135 45
50 0x32C5C 150 50
55 0x32C66 165 55
60 0x32C70 180 60
65 0x32C7B 195 65
70 0x32C84 210 70

Note: The REFCLK values shown in the table above are just a simple example and the user must be aware that depending on the application running some REFCLK values might not guarantee the correct behavior of the system.

Article last edited on: 2009-09-17 10:45:48

Rate this article

[Bad]
|
|
[Good]
Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Link to this article
Copyright © 2011 ARM Limited. All rights reserved. External (Open), Non-Confidential