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Applies to: ARMv7 Architecture
The v7-A/R architecture provides support for unalgined accesses (LDR/STR) to memory regions marked as Normal. Unalgined accesses to address regions marked as Device or Strongly Ordered will result in an abort.
The Cortex-A family of cores treat all data accesses as Strongly Ordered when the MMU is disabled. So to allow unaligned accesses you must first enable the MMU, and have the required address region(s) marked as Normal. Example MMU initialization code is provided with RVDS.
Unaligned accesses can also be caught by setting the A bit in the CP15 Control register.
Article last edited on: 2009-09-17 09:03:39
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