|ARM Technical Support Knowledge Articles|
This knowledge article provides example initialization code for the Cortex-A9 MPCore and Cortex-A5 MPCore. The example implements a simple bare metal SMP program, and demonstrates how to enable and configure the MPCore's hardware features.
The example includes code for configuring the Interrupt Controller, SCU, MMU, caches, and branch predictor.
The intention of this example is to be readable and easy to follow, not provide optimal performance. The example is not modelled on an operating system, and does not use threads.
This example can be run on:
This code is provided as an example only, and comes with no support entitlement. It requires RVDS 4.1 SP1 Professional to build.
The example includes a readme file which describes how to build and run the example. The readme also describes the structure of the example.
Article last edited on: 2010-12-01 15:47:52
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