What are the LT-XC5V (Virtex-5) Logic Tile I/O connections?

[New, 22 Sep 2009]

The diagram attached to this article shows FPGA I/O connections for the Virtex-5 Logic Tile. The FPGA banks are shared between upper headers (XU, YU, ZU, Z) for communication with a top Logic Tile or daughter card, and lower headers (XL, YL, ZL, Z) for communication with a baseboard or bottom Logic Tile.

The I/O communication between FPGAs in a stack of Logic Tiles is significantly increased using configurable switches (upper fold, lower fold, thru):

• Upper fold-over allows routing of FPGA I/O signals to spare lower header pins not normally routed to FPGA I/Os.
• Lower fold-over allows routing of FPGA I/O signals to spare upper header pins not normally routed to FPGA I/Os.
• Thru allows bypassing a Logic Tile FPGA I/O via spare upper/lower header pins not normally routed to FPGA I/O.