|ARM Technical Support Knowledge Articles|
Applies to: Debug Access Port (DAP)
With a JTAG-AP, the frequency of CSTCK can be up to one sixth of the frequency of the internal DAP bus (DAPCLK), so for a 100+ MHz DAPCLK, that could mean a CSTCK of 20+ MHz. This may be too fast for some JTAG devices. ARM9 and ARM11 subsystems generate RTCK, which can be used for adaptive control of the CSTCK frequency, but ARM7 and possibly non-ARM JTAG devices don't generate RTCK.
For subsystems which require a slower CSTCK but do not provide a CSRTCK adaptive return clock, you can slow CSTCK by adding some logic between CSTCK and CSRTCK clocked by DAPCLK. This should be a counter, or a sequence of flops, so that when CSTCK goes high, CSRTCK will go high n cycles later. Once this happens, CSTCK will go low after some delay, and the counter can then count down again so that CSRTCK will go low n cycles later.
You should try to keep the CSRTCK duty cycle as close to 50% as possible, and should therefore end up with waves looking something like:
CSTCK __| |________| |_
CSRTCK _____| |________|
CSRTCK is shown lagging CSTCK by almost 180 degrees, on the assumption that DAPCLK might be several times faster than CSTCK, so CSRTCK edges will be sampled by the JTAG-AP soon after they occur, and a new CSTCK edge generated.
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