|ARM Technical Support Knowledge Articles|
Applies to: ARM926EJ-S
In the cp15 c1 register, bits I and M control the enabling of the I and D caches respectively. At reset the value of these bits is 0 so both I and D cache are disabled.
See Chapter 4 "Caches and Write Buffer" in the TRM for full details.
Article last edited on: 2009-10-05 11:53:45
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