ARM Technical Support Knowledge Articles

Can the Cortex-R4 perform unaligned instruction fetches on the AXI-M interface?

Applies to: Cortex-R4


No, instruction fetches on the AXI-M interface always have a 64-bit transfer size (ARSIZE) and are always to 64-bit aligned addresses (ARADDR), even though the instructions themselves may be unaligned.

Rate this article

Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Link to this article
Copyright © 2011 ARM Limited. All rights reserved. External (Open), Non-Confidential