ARM Technical Support Knowledge Articles

Can the Cortex-R4 perform unaligned instruction fetches on the AXI-M interface?

Applies to: Cortex-R4

Answer

No, instruction fetches on the AXI-M interface always have a 64-bit transfer size (ARSIZE) and are always to 64-bit aligned addresses (ARADDR), even though the instructions themselves may be unaligned.

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