|ARM Technical Support Knowledge Articles|
Applies to: PL330 AXI DMA Controller
Unlike PL080, ARM's previous incarnation of the DMA controller, PL330 places no restrictions on the relationship between the source and
destination burst quantities, other than unaligned transfers and endian swap size functionality, both of which are documented in sections 2.11.1
and 2.11.2 of the TRM.
For example, with PL330, the source could write some data to PL330. This could be read, after a long time, by the destination over a period of time. In addition, the data need not even be read out at all. PL330 gives this 'freedom' for the source and destination to decide what the transfer of data has to be. Data that is not read out by the destination sits in the MFIFO in PL330 and gets overwritten eventually. The MFIFO is actually a buffer which is used to store the data before sending it to the destination.
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