|ARM Technical Support Knowledge Articles|
Applies to: ARM926EJ-S
I have been comparing an ARM926EJ-S and an ARM7TDMI, both running at approx. 27MHz and with the ARM926EJ-S's cache turned off. The ARM926EJ-S runs considerably slower than the ARM7TDMI. Why?
An ARM7TDMI does not have a cache, therefore it is optimised to run at memory speeds - the 27MHz you mention - and get the best out of single-cycle-access memory at those speeds. As a cached processor, the ARM926EJ-S is optimised to run with the cache enabled - indeed it is recommended that the cache is enabled as soon as possible after boot - and will, unfortunately, run very inefficiently without the cache, especially at comparable speeds to the ARM7TDMI. This is because the ARM926EJ-S will still 'access' the cache even though it is disabled as it sits between the core and L2 memory. To get the best out of the ARM926EJ-S you really ought to be running it with the cache enabled and at more like 200MHz. This way, the ARM926EJ-S can make proper use of its cache.
Other things to bear in mind are whether you are using the cache properly. Caches work best with code loops that fit in neatly. If a code loop, say, spans multiple cache lines or otherwise doesn't fit neatly, then the cache will be constantly fetching and flushing - 'thrashing'. The same applies if the code has to fetch data that is located in various places scattered in memory.
Did you find this article helpful? Yes No
How can we improve this article?