ARM Technical Support Knowledge Articles

What is the purpose of the PL022 IMSC, RIS, MIS and ICR registers?

Applies to: PL022 Synchronous Serial Interface


Interrupt mask set and clear register - SSPIMSC

This register allows the programmer to determine whether an interrupt is generated, i.e. whether the interrupt becomes 'visible' outside the SSP.
An interrupt is only generated when IMSC[interrupt] & RIS[interrupt] == 1.

Raw interrupt status register - SSPRIS

This is the current state of the interrupt BEFORE masking. If an interrupt source subsequently goes away, this will be reflected in this bit (RIS[interrupt] 1 -> 0).

Masked interrupt status register - SSPMIS

This is the current state of the interrupt AFTER masking. It is RIS[interrupt] & IMSC[interrupt]. It is effectively the current state of the interrupt; if either the interrupt goes away or the mask is cleared then the Masked Interrupt is also cleared.

Interrupt clear register - SSPICR

This register allows interrupts to be cleared. Clearing ICR[interrupt] will clear the interrupt and therefore both RIS[interrupt] and MIS[interrupt].

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