ARM Technical Support Knowledge Articles

Why do I see ETM FIFO overflow errors when using ETB trace capture mode in RVD?

Applies to: RealView Development Suite (RVDS)


This article only applies to hardware targets based on the CoreSight debug and trace architecture, and which implement both an Embedded Trace Buffer (ETB) and Trace Port Interface Unit (TPIU).


RVD does not currently disable the TPIU when performing ETB trace.

When having an enabled TPIU component on a target (when performing ETB trace), it will restrict the packet rate of the ETM and as a result cause ETM FIFO overflows.

The solution is to manually stop the TPIU formatter before starting your ETB trace session in RVD.  This can be done by writing to the TPIU Formatter and Flush Control Register (FFCR).  The following steps are required:

  1. Connect to the ‘CSTPIU’ component using the ‘Connect to Target’ window in RVD
  2. In the RVD register window set ‘CSTPIU FFCR’ to 0x1000
    (setreg @CSTPIU_FFCR=0x00001000)
  3. In the RVD register window set ‘CSTPIU FFCR’ to 0x1040
    (setreg @CSTPIU_FFCR=0x00001040)
  4. Disconnect from the ‘CSTPIU’
  5. Follow the normal connection and setup procedure for  ETB trace


Hardware targets with ARM processors implementing an Embedded Trace Macrocell (ETM) can produce a real-time trace stream of instruction and data processed by the core.  The trace stream can be captured in an on-chip ETB or via the TPIU in an off-chip trace capture unit like RealView Trace (RVT). The RealView Debugger (RVD) supports both these trace capture modes.

Refer to the CoreSight Technical Reference Manual for details on trace components discussed below:

On a hardware target with both a CoreSight ETB and TPIU, the trace steam from the core (ETM) must be routed to both destinations. This is typically achieved using a CoreSight Replicator component.

The typical post-reset behaviour of a CoreSight target has both the ETB and TPIU enabled, ready to receive packets from a trace source (e.g. ETM) over the AMBA Trace Bus (ATB). Trace packets can only be sent when all receiving (TPIU and ETB) components acknowledge that they are ready to receive more trace data.

The ETB has a 32-bit interface for capturing trace while the default external port size of the TPIU is 1-bit. The TPIU trace port clock is normally slower compared to the ETB clock. The result is that the TPIU will typically process data much slower than the ETB.

The ETM packet rate will be limited by the slowest receiving component. In the situation described above, the TPIU (in post-reset state) will restrict the ETM output rate to such an extent that the internal FIFO buffer (in the ETM) will repeatedly overflow.

In ETB trace mode the TPIU must be disabled to prevent it limiting the bandwidth between the ETM and ETB. The following writes are required to stop the TPIU formatter.

TPIU.FFCR = 0x1000 (Stop formatter on manual flush enabled)
TPIU.FFCR = 0x1040 (Manual flush request)

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