ARM Technical Support Knowledge Articles

Benefits of PL310 r3p0 Data RAM banking

Applies to: AXI PL310 L2CC


From the TRM:

Timing closure is difficult with designs that have a high clock frequency and large L2 cache, especially for the data RAM. Such systems require high RAM latencies, which reduces the performance of the system. To counter this effect, you can split the data RAM into four banks. This feature enables pipelined accesses to the data RAM.

The Data RAM is slightly over 10 times larger than the Tag RAM and so is likely to have a higher latency than the Tag RAM.  Large RAMs have higher latencies, and so Data RAM banking was introduced to allow the Data RAM to be split into 4 smaller banks, which should improve latency.  An additional benefit of banking is that it allows pipelined accesses to the Data RAM.

So if you find that the latency of your unbanked large Data RAM is the same or lower than that of your Tag RAM (it is extremely unlikely that it would be lower - if it is then you should select a different Tag RAM from your library) then banking is not likely to offer you performance benefits.

You should decide, based on the performance characteristics of your RAM, whether Data RAM banking offers the potential for performance improvement in your PL310 implementation.

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