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Applies to: CTR4
On the EB+CT-R4F system the default CPU clock frequency is 250Mhz and the default AXI bus frequency is 38Mhz.
These values have been selected to provide the highest performance whilst keeping system stability, however users often want to change the default clock settings for benchmarking, test purposes, etc.
An inappropriate procedure to change the clock settings can lead to system lock-up problems and as a consequence the need to issue a hardware reset for system recovery.
In this Knowledge Article we discuss some alternative methods that can be used to change the clock settings safely.
The EB system uses five programmable clock generators (oscillators) that provide reference frequencies to different components on board. Please refer to the EB User Guide for a description of the EB clocks.
The CT-R4F provides five external clocks for the ARM Cortex-R4F test chip. Please refer to the CT-R4F User Guide for a description of the CT-R4F clocks.
Following are the possible methods to control the CPU frequency on an EB+CT-R4F system. For both methods, a debugger like RVD needs to be used to set the correspondent registers.
This method consists on modifying the PLL0 settings on the Test Chip. For that, a specific R4F Test Chip serial configuration register needs to be set accordingly to the parameters M and N that you need to modify to obtain a specific CPU frequency. This register must be set through a EB system register, CT_R4F_TC_CFG0.
For more information on the CT_R4F_TC_CFGx registers please refer to AN217, which is available from the ARM Website:
The CPU frequency is calculated according to the following formula:
CPUCLK=REFCLK x M/N
Where REFCLK is the reference clock for the CPU. It is generated by the CT-R4F oscillator OSC0 and the default is 50MHz.
The following sequence is an example to change the M and N parameters of PLL0:
The following table shows some example register configurations for different M and N values.
This method consists on varying the reference clock for the PLL0. It requires manual configuration of the oscillators registers, SYS_OSCRESETx, in order to vary the frequency of OSCCLK0 which output is the reference clock for PLL0. The following sequence is an example to change the reference clock for the CPU:
The following table shows some example register configurations for different reference frequencies.
IMPORTANT NOTE: The reference values and parameters shown in the tables above are just a simple example and the user must be aware that depending on the application running some values might not guarantee the correct behavior of the system.
Article last edited on: 2009-12-18 13:11:25
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