|ARM Technical Support Knowledge Articles|
Applies to: Cortex-R4
No, you cannot execute code from Strongly Ordered or Device memory - it has to be cacheable or non-cacheable Normal memory. If you configure the region as SO, the MPU will abort as soon as it is enabled.
The TRM says on page 7-5:
"Instructions cannot be executed from regions with Device or Strongly-Ordered memory type attributes. The processor treats such regions as if they have XN permissions."
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