|ARM Technical Support Knowledge Articles|
Applies to: ARM1176
The SIZE will depend on the transfer size (TS) parameter in the control register, if the memory
type is device/strongly ordered. Size may be modified for normal memory to make use of more
efficient 64-bit transfers.
BURST will be INCR or, if the stride is zero, will be FIXED for accessing FIFOs.
LEN depends on the size of the DMA data buffer. It is possible to transfer up to 8 words in a
burst, so bursts can be 4 beats of 64 bits.
Address will be aligned to the size of the transfer.
SIZE : 1, 2, 4, 8 bytes
BURST : INCR or FIXED
LEN : 0-3 (i.e. up to 4 beats)
ADDR: aligned to the SIZE
Consider a DMA transfer with TS = 2 bytes, stride = 2 bytes.
If the memory type is normal, the transfer is done using 64bit sized transfers, 4-beat burst
If the memory type is DEVICE, the transfer is done using 16bit sized transfers, single (LEN=0).
Did you find this article helpful? Yes No
How can we improve this article?