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Cortex-A9 MPCore cached Dhrystone examples for Versatile Express

Applies to: Cortex-A9, V2P-CA9

Answer

Overview

The attached archive contains four cached Dhrystone examples that run on a Cortex-A9 MPCore and by default configure a PL310 Level 2 cache on the SoC. The examples must be run under a Debugger that supports Semihosting, such as RealView Debugger.

The examples are written to run on ARM's A9 Versatile Express development board. However, the only SoC-specific device used is the PL310 and so the examples can be easily ported to a different target. See 'Building the examples for different targets' below.

Example 1 is the simplest example. Only CPU0 runs Dhrystone, the other CPUs are placed in Wait For Interrupt (WFI).

Example 2 runs Dhrystone on up to four CPUs in parallel with different cacheable attributes:

  1. 0x00100000 DHRY_0 Outer cacheable, Inner cacheable
  2. 0x00200000 DHRY_1 Outer cacheable, Inner non-cacheable
  3. 0x00300000 DHRY_2 Outer non-cacheable, Inner cacheable
  4. 0x00400000 DHRY_3 Outer non-cacheable, Inner non-cacheable

The resulting DMIPS figures prove that Dhrystone is executed from the L1 cache for CPU0 and CPU2, L2 cache for CPU1 and L3 memory for CPU3.

Example 3 significantly extends Example 2 to use the built-in Cortex-A9 MPCore Timers to measure time, rather than semihosted time. This adds interrupt handling and further GIC/CPU interface configuration to the example.

Example 4 is a redesign of Example 3.

Further information is provided in the README files included with each example and through comments in the code.

Building & running the examples

Each example includes a build.bat file that generates AS_C-A9MP_PL310_Dhry_Ex<n>.axf. This image should be loaded through a Debugger onto all CPUs within the Cortex-A9 MPCore. The Debugger must support Semihosting, see How do I configure semihosting in RVD?

When running the multicore examples, please ensure that CPU0 is started after the other CPUs. The target should be reset before running each example since they assume that all caches are disabled.

Building the examples for different targets

Each example includes one or more 'scatter' (linker description) files. These can be edited to change the:

If your system does not include a PL310 cache then you must add -DNO_PL310 to the compiler arguments.

Attachments: AS_C-A9MP_PL310_Dhry.zip

Article last edited on: 2012-05-28 10:42:23

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