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Applies to: PL08x DMAC (DM & SM)
The 'Big Endianness' of PL080/081 is intended for byte transfer between big and little endian systems, such as networking systems. When BE is selected for a master interface in the DMACConfiguration register, it performs a byte swap on the data as it enters, or leaves, the DMAC. If you are using a single master for data transfer in BE mode then data will be byte swapped (to Little Endian) on reading and again (back to Big Endian) on writing. This is fine if both source and destination memory systems are BE.
If you are using both masters, say in a system converting BE to LE data, then the data will be byte swapped on reading from the BE system but not when writing to the LE system, and vice versa.
If you are using LLIs to perform scatter-gather operations then this can cause problems. If the LLI data is stored in a BE memory system it will be converted to LE on being read by the DMAC. This is because the data for the LLIs is being read from a BE memory system and then byte-swapped to LE before being stored in the internal LLI registers. Problems now arise because the source address, destination address, control information and next LLI address are now in a swapped endian format.
There are two ways round this:
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