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Reads from DWT registers return unexpected values

Applies to: Cortex-M3

Answer

The Data Watchpoint and Trace counter registers DWT_CYCNT, DWT_CPICNT, DWT_EXCNT, DWT_SLEEPCNT, DWT_LSUCNT, DWT_FOLDCNT, DWT_PCSR can only be accessed when the TRCENA bit in the Debug Exception and Monitor Control Register ( DEMCR[24] ) is set.

From the DEMCR definition:

[24] Read/write TRCENA - This bit must be set to 1 to enable use of the trace and debug blocks:
• Data Watchpoint and Trace (DWT)
• Instrumentation Trace Macrocell (ITM)
• Embedded Trace Macrocell (ETM)
• Trace Port Interface Unit (TPIU).

If the TRCENA bit is not set, reads from the DWT counters return an unpredictable value which may be related to previous activity.

For example, if the DWT registers are read in order while TRCENA is clear, starting from DWT_CTRL, the counter register reads may return the value previously read from DWT_CTRL:

#   DEMCR = 00000000
#
#   DWT_CTRL = 40000000
#   DWT_CYCCNT = 40000000
#   DWT_CPICNT = 40000000
#   DWT_EXCCNT = 40000000
#   DWT_SLEEPCNT = 40000000
#   DWT_LSUCNT = 40000000
#   DWT_FOLDCNT = 40000000
#   DWT_PCSR = 40000000
#
#   DEMCR = 01000000
#
#   DWT_CTRL = 40000000
#   DWT_CYCCNT = 0
#   DWT_CPICNT = 0
#   DWT_EXCCNT = 0
#   DWT_SLEEPCNT = 0
#   DWT_LSUCNT = 0
#   DWT_FOLDCNT = 0
#   DWT_PCSR = 57a

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