|ARM Technical Support Knowledge Articles|
Applies to: PL341 AXI DDRII Dynamic Memory Controller
The assumption is that all memories connected to DMC-34x are of the same type and therefore the same refresh period. This is why there is only a single refresh_prd register and hence all refresh timings for each memory chip connected to DMC-34x are same. It is therefore not possible to set individual chip refresh timing periods.
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