ARM Technical Support Knowledge Articles

Accessing Cortex-A9MP's global timer causes abort

Applies to: ARMv7 Architecture, Cortex-A9

Answer

Cortex-A9 MPCore contains a 64-bit global timer peripheral. The 64-bit count register is readable and writeable, but it is normally not intended to be read by application code. Instead, it is primarily targetted for use by an operating system's task scheduler.

However, when performing read access to the 64-bit global timer, the programmer may naturally define a long long data type to refer to the timer peripheral address, and expect a LDRD or LDM instruction to access the address. Be aware that LDRD/LDM will cause data abort. A recommendation is to use embedded assembler to write the accessing code in assembly. For details of accessing the global timer registers, please see the Cortex-A9 MPCore's TRM.

Rate this article

[Bad]
|
|
[Good]
Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Link to this article
Copyright © 2011 ARM Limited. All rights reserved. External (Open), Non-Confidential