|ARM Technical Support Knowledge Articles|
Cortex-A9 MPCore contains a 64-bit global timer peripheral. The 64-bit count register is readable and writeable, but it is normally not intended to be read by application code. Instead, it is primarily targetted for use by an operating system's task scheduler.
However, when performing read access to the 64-bit global timer, the programmer may naturally define a
long long data type to refer to the timer peripheral address, and expect a LDRD or LDM instruction to access the address. Be aware that LDRD/LDM will cause data abort. A recommendation is to use embedded assembler to write the accessing code in assembly. For details of accessing the global timer registers, please see the Cortex-A9 MPCore's TRM.
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