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Is the ARM Compiler and RVCT able to workaround the Cortex-M3 errata 602117?

Applies to: DS-5, RealView Development Suite (RVDS)


The document PR141-PRDC-007452 v10.0 - Errata notice on Cortex-M3, presents workarounds for errata 602117.

"602117: LDRD with base in list may result in incorrect base register when interrupted or faulted"

In general, it is recommended to use workaround 1, which presents a way to write LDRD instructions in order to avoid the triggering condition. However, when using a C/C++ Compiler, this is not an ideal workaround. So is the ARM Compiler able to workaround errata 602117?


All compiler vendors should have been notified about this errata. And this form of LDRD instruction should be avoided by most compilers.

ARM Compiler 4.1 and 5.x are able to avoid generating those instructions. In RVCT 3.1 build 761 or later and RVCT 4.0 build 471 or later, the RVCT C/C++ libraries have also been rebuilt to avoid these instructions.  Note that since this is Cortex-M3 specific, this compiler workaround can be only realized when --cpu=Cortex-M3 is specified.

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