ARM Technical Support Knowledge Articles

Why is the "T" bit 0 when I load my program to a Cortex-M0 or Cortex-M3 processor?

Applies to: RealView Development Suite (RVDS)

Answer

The "T" bit in the Combined Program Status Register (XPSR) indicates the execution state of the ARM core. ARM v6-M and v7-M processors such as the Cortex-M0 and Cortex-M3 can only execute in Thumb state and should always have the "T" bit equal to 1. However, the v6-M and v7-M architectures still allow the "T" bit to be set to 0.

When a program is loaded to a Cortex-M0 or Cortex-M3 processor, RealView Debugger (RVD) will not modify the "T" bit. On a core reset or power-on reset, the "T" bit will be set to the least-significant bit (LSB) of the value of the Reset Vector at address 0x4. All entries in the Vector Table must have the LSB set so the processor will execute the exception handler in Thumb state.

If you have an invalid Reset Vector address or have not programmed the vector table, it is possible that when you connect to the processor the "T" bit will be 0. If you then load your image and try to execute it, you will receive an error from RVD such as one of the following:

Error V2801C (Vehicle): 0x05060012: Target in wrong state/mode.

Error: 0x021d0102: Error Attempt to go without Thumb state set in xPSR from target : Cortex-M0_0.

To resolve this error, you can program a valid Vector Table to memory and reset the processor. This will force the "T" bit to 1 if the Reset Vector is valid. If you are unable to program a valid Vector Table, you can manually set the "T" bit to 1. On the Cortex-M0 you must do this from the command line:

 setreg @XPSR=0x01000000

On the Cortex-M3 you can either do this through the command line using the above command, or use the Registers pane to modify the XPSR.

Article last edited on: 2010-04-09 20:51:22

Rate this article

[Bad]
|
|
[Good]
Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Link to this article
Copyright © 2011 ARM Limited. All rights reserved. External (Open), Non-Confidential