Can I place APB system peripherals in the External Private Peripheral Bus (External PPB) space?
Applies to: Cortex-M3, Cortex-M4
Answer
The External PPB (EPPB) space (0xE0040000 up to 0xE0100000) is intended for CoreSight-compatible debug and trace components, and has a number of irregular limitations which make it less useful for regular system peripherals. ARM recommends that system peripherals are placed in suitable (Device type) areas of the System bus address space, with use of an AHB2APB bridge (protocol converter) for APB-based devices.
Limitations of the EPPB space are:
- it is accessible in privileged mode only
- it is accessed in little-endian fashion irrespective of the processor's data endianness setting
- accesses behave as Strongly Ordered
- no bit-band function is available
- unaligned accesses have unpredictable results
- only 32-bit data accesses are supported
- it is accessible from the Debug Port and the local processor, but not from any other agent (processor) in the system
Use of regular System space and an AHB2APB bridge for system peripherals removes most of these restrictions and causes the peripheral accesses to behave as a user would expect.
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