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Can I boot Linux in the Normal world on the Cortex-A8 EB RTSM?

Applies to: Fast Models, RealView Development Suite (RVDS)

Answer

Booting Linux in the Normal world requires a number of additional configuration steps.  In a real system, these steps would be carried out by the boot code in the Secure world.  When working with the RTSM the steps can be done in the RVD GUI.

Note 1: The EB RTSMs do not provide a secure memory system. The core can be used in the Normal world, but the memory system will not provide any protection. 
Note 2: This Knowledge article concentrates on the Cortex-A8 EB RTSM.  The steps would be similar for the Cortex-A9 RTSM. 

System Configuration

The system has to be configured to allow non-secure (NS) access to the peripherals and memory used by Linux. 

Interrupt controller

The EB RTSMs include a PL390 Interrupt Controller, which implements the Generic Interrupt Controller (GIC) Architecture. The GIC Architecture includes security extensions for supporting TrustZone systems. To receive interrupts in the Normal world two additional registers need to be configured.  This must be done while still in the Secure world.

Interrupt Security Registers (ICDISR{n})
This register is used to set which interrupt IDs are available in the Normal world

Interrupt Priority Mask Register (ICCPMR)
The Priority Mask register is shared between the Normal and Secure world. Before the Normal world can access the register, the Secure world MUST write a value greater than 0x80 to it.  Refer to section 4.2.1 (Non-secure access to register fields for Secure interrupt priorities) of the GIC Architecture (ARM IHI 0048A) for an explanation.

Memory Map

Most TrustZone enabled systems will include a TrustZone Protection Controller (TZPC) or similar. This is used to set which address regions are accessible in the Normal world. This must be configured before entering the Normal world. The RTSMs do _not_ include a TZPC, so this step can be skipped.

CPU Specific

CP15 includes three TrustZone configuration registers.

Non-secure Access Control Register (NSACR)
This register controls Normal world access to coprocessors (such as VFP and NEON) and TLB lock down.  On the Cortex-A8 it also controls access to the PLE and L2 cache lock down.  On the Cortex-A9/A5 it controls access to the ACTLR.SMP bit.

For Linux to boot you should enable access to at least the VFP and NEON (if Linux was built to use them).

Secure Debug Enable Register (SCR)
This register controls debug access.  It is not required to change the default value to boot Linux on the RTSMs.

Secure Configuration Register (SCR)
This register controls exception behaviour, and which world the core is currently in (NS bit).  The NS bit must be set to switch the core into the Normal world.  This step must be done after all the other configuration steps.

RVD

In RVD you can perform the required operations for the Cortex-A8 EB RTSM with the following commands:

    ce ((unsigned long *)S:0x10040004)[0]=0x80
  ce ((unsigned long *)S:0x10041080)[0]=0xF000FFFF
  ce ((unsigned long *)S:0x10041084)[0]=0xFFFFFFFF
  setreg @CP15_SECURE_DEBUG_ENABLE=0x00000003
  setreg @CP15_SECURE_CONFIGURATION_NS=0x00000001

The core is now in the Normal world, with the GIC configured to allow Normal world interrupts.  Now follow the steps in:

  Can I boot the Linux kernel on the RTSMs provided with RVDS?

Article last edited on: 2013-01-04 16:07:34

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