|ARM Technical Support Knowledge Articles|
Applies to: Cortex-M3
Architectural clock gating in the RTL is a configurable option in all versions of Cortex-M3.
In r1p1, it is controlled by several `defines, descriptions of which licensees of the RTL can find in the Implementation Guide.
//`define CLOCKGATE 1
//`define INTEGRATION_CLOCKGATE 1
//`define ETM_CLOCKGATE 1
//`define CORE_CLOCKGATE 1
In r2p0 it is controlled by the single CLKGATE_PRESENT parameter for each instantiation of the Cortex-M3, as described in the Cortex-M3 Integration and Implementation Manual available to RTL licensees.
The clock gating is invisible from the programmer's point of view, so it is not described in the Technical Reference Manual (TRM). Control of the clock gating is inferred from the circuit activity.
To minimize power consumption, ARM recommends the use of both architectural clock gating and leaf cell clock gating inferred by synthesis tools for ASIC (chip) implementation by RTL licensees. For FPGA prototyping, clock gating can cause some difficulty and inconvenience, and as the benefit is relatively small in FPGA prototypes, it makes sense to de-configure clock gating in this case.
Did you find this article helpful? Yes No
How can we improve this article?