|ARM Technical Support Knowledge Articles|
Applies to: Cortex-M3
The INTISR signals cause asynchronous interrupts, but the INTISR signals must be driven synchronous to HCLK and must meet setup and hold requirements.
If you drive INTISR from off chip or from an asynchronous clock domain, you must synchronize it to HCLK before driving INTISR into CortexM3.v.
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