ARM Technical Support Knowledge Articles

I am confused about the PARTNO value in the IDCODE of my CoreSight DAP's Debug Port

Applies to: DAPLITE, Debug Access Port (DAP)

Scenario

The ARM Debug Interface v5 Architecture Specification (ADIv5) revision 'A' contains:

[27:12] PARTNO Part Number for the DP. This value is provided by the designer of the Debug Port and must not be changed. Current DPs designed by ARM Limited have the following PARTNO values:
JTAG-DP 0xBA00
SW-DP 0xBA10

The CoreSight Components Technical Reference Manual (TRM) revision 'H' contains:

[27:12] PARTNO Part Number for the debug port. This value is provided by the designer of the Debug Port and must not be changed. Current ARM-designed debug ports have the following PARTNO values:
JTAG-DP 0xBA00
SW-DP 0xBA02

The SW-DP part numbers are inconsistent.

Answer

There is a supplementary document which should be read in conjunction with the ADIv5, entitled "ARM® Debug Interface v5 Architecture Specification ADIv5.1 Supplement" (ADIv5.1), document number DSA09-PRDC-008772.

The ADIv5.1 document contains:
- errata for the ADIv5 document
- extensions to the ADIv5 Architecture

The code 0xBA10 for the SW-DP IDCODE PARTNO is a typographical error in the ADIv5, as noted in the errata section of ADIv5.1.

The ADIv5.1 introduces the concept of Multi-drop Serial Wire, where a single Serial Wire Debug (SWD) port can identify and control mutliple SW-DPs over a single Serial Wire connection.

The ADIv5.1 refines the definition of the IDCODE bitfields within the range [27:12].

For JTAG-DPs, the PARTNO field remains IDCODE[27:12] = 0xBA00 for all current JTAG-DPs.

For SW-DPs, the corresponding bitfield is now split out into:
IDCODE[27:20] = PARTNO = 0xBA
IDCODE[19:17] = unknown
IDCODE[18] = M (Minimal) = 0 for regular DPs, 1 for reduced functionality DPs
IDCODE[15:12] = VERSION
The VERSION field currently takes one of the following values:
0x1 : version 1 SW-DP, supporting a single SW-DP per SWD port
0x2 : version 2 SW-DP, supporting Muti-drop

A zipfile containing both documents (pdf) can be downloaded by registered users from ARM's "silver" service ( https://silver.arm.com ) under:

Documentation ->
  CoreSight on-chip trace & debug ->
    Architecture Specifications ->
      ARM Debug Interface v5 ->
        PDF version

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