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The first edition of the LogicTile Express V2F-1XV5 TRM (DUI0449A ID112709) contains a block diagram which makes reference to an I2S block inside the FPGA (Figure 2-5):
The text contains no reference to this IP block, nor where its signals terminate on the V2M-P1 motherboard. This Knowledge Article clarifies this omission. It also answers the related question - "What is the pinout of the V2M-P1 DVI connector?"
Background info on I2S
Also written as I2S, and expanded to Inter-IC Sound or Integrated Interchip Sound. This refers to a synchronous serial bus interface which is used to carry digital audio data between board components. An explanation of the I2S protocol is beyond the scope of this Knowledge Article.
The I2S controller shown in the diagram does not exist in any of the example FPGA logic that ARM supplies with the board. ARM cannot provide an I2S controller reference design. This block is shown in the diagram merely to demonstrate that such a controller could be instantiated in the user's design if required. The DVD supplied with the board contains an Applications Note (AN224) which goes so far as to define the pins for the MMB_* signals that would connect such a block to the V2M-P1 motherboard, but they are left unconnected inside the FPGA.
These digital audio pins are routed from the LogicTile, across the MMB (Multi Media Bus) to the DVI MUX on the V2M-P1 motherboard. The MMB multiplexor selects whether the Sil9022 DVI interface IC on the motherboard is driven from a peripheral in the motherboard FPGA, or Tile Site 1, or Tile Site 2. The V2M-P1 TRM describes the MUX operation - please refer to the section entitled "Hardware Description".
If the LogicTile is selected as a source, the MMB pins to the DVI subsystem are assigned as such:
net name pin pin
MMB_SCLK G12 F8
MMB_SD P12 F9
MMB_SD N11 G8
MMB_SD P10 F10
MMB_SD H13 H8
MMB_WS J10 E8
When the LT is selected as the DVI source, the MMB pins listed above are connected to the similarly named pins on the Sil9022 DVI Transmitter IC on the motherboard, which is in turn connected to the DVI connector on the V2M-P1 rear panel. For details of the operation of the DVI chipset, the chip manufacturer's datasheet should be consulted:
For reference, the DVI pinout on the V2M-P1 is this:
1 DVI_TX2N 13 N/C C1 V_RED
2 DVI_TX2P 14 5VFUSED C2 V_GREEN
3 DVI_GND 15 DVI_GND C3 V_BLUE
4 N/C 16 DVI_HPDO C4 V_HSYNC
5 N/C 17 DVI_TX0N C5 VGA_GND
6 DVI_DSCLO 18 DVI_TX0P
7 DVI_DSDAO 19 DVI_GND
8 V_VSYNC 20 N/C
9 DVI_TX1N 21 N/C
10 DVI_TX1P 22 DVI_GND
11 DVI_GND 23 DVI_TXCP
12 N/C 24 DVI_TXCN
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