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What does L210 do with AXI IDs when disabled?

Applies to: AXI PL310 L2CC

Answer

When disabled, PL310 treats all accesses as Strongly Ordered, i.e. non-cacheable and non-bufferable. The following tables indicate the various options:

This table shows the format of the IDs that are exported on the master ports for writes:


Master ID buses       Access types                       ID value, Verilog
===============       ============                       =================
AWIDMx, WIDMx, BIDMx  Non-bufferable write from slave 0  {AWIDS0, 00}
                      Non-bufferable write from slave 1  {AWIDS1, 10}
                      Eviction from slot 0               {{`pl310_AXI_ID_MAX-1{0}, 0011}
                      Eviction from slot 1               {{`pl310_AXI_ID_MAX-1{0}, 0111}
                      Eviction from slot 2               {{`pl310_AXI_ID_MAX-1{0}, 1011}
                      Device write from store buffer     {{`pl310_AXI_ID_MAX-1{0}, 1101}
                      Write from store buffer slot 0     {{`pl310_AXI_ID_MAX-1{0}, 0001}
                      Write from store buffer slot 1     {{`pl310_AXI_ID_MAX-1{0}, 0101}
                      Write from store buffer slot 2     {{`pl310_AXI_ID_MAX-1{0}, 1001}


This table shows the format of the identifications that are exported on the master ports for reads.

Master ID buses Access types                                             ID value, Verilog
=============== ============                                             =================
ARIDMx, RIDMx   Non-cacheable exclusive or locked read from slave 0      {ARIDS0, 00}
-               Non-cacheable exclusive or locked read from slave 1      {ARIDS1, 10}
-               Read from store buffer slot 0                            {{`pl310_AXI_ID_MAX-1{0}, 0101}
-               Read from store buffer slot 1                            {{`pl310_AXI_ID_MAX-1{0}, 1001}
-               Read from store buffer slot 2                            {{`pl310_AXI_ID_MAX-1{0}, 1101}
-               Prefetch from linefill buffer slot 0                     {{`pl310_AXI_ID_MAX-2{0}, 10011}
-               Prefetch from linefill buffer slot 1                     {{`pl310_AXI_ID_MAX-2{0}, 10111}
-               Prefetch from linefill buffer slot 2                     {{`pl310_AXI_ID_MAX-2{0}, 11011}
-               Prefetch from linefill buffer slot 3                     {{`pl310_AXI_ID_MAX-2{0}, 11111}
-               Non-cacheable reads and linefill generated by cacheable read miss from slave S0 or S1[a]
                                                                         {{`pl310_AXI_ID_MAX-1{0}, 0011 | 0111 | 1011 | 1111}

As you can see from the above tables, when the PL310 is disabled:

* all write Ids should be passed through untouched
* exclusive or LOCKed read Ids should be passed through untouched
* all other reads may be changed to some other value

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