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Applies to: Cortex-A5
The Cortex-A5 has a hardware mechanism for reset of the instruction cache, data cache and TLB.
This mechanism is enabled by default at reset and can be disabled by holding the L1RSTDISABLE signal high while reset is deasserted. Use of L1RSTDISABLE would be appropriate when returning from dormant state in order to preserve memory contents.
The mechanism for initialising the caches and TLB is to write to the valid bits to indicate the entry is invalid. In the case of the I$, this is the 2 MSBs (bits 23,22) of the TAG RAM and both bits are set to 1. In the case of the D$, all bits of the TAG RAM are written to 0. In the case of the TLB, bit 0 is written to 0.
The I$ has between 64 and 1024 entries, depending on the cache size. So it takes 64-1024 clock cycles to initialise the I$. I$ is organised as 2 banks.
The D$ has between 32-512 entries, depending on cache size, so it takes 32-512 clock cycles to initialse the D$. D$ is organised as 4 banks.
TLB has 128 entries in 2 banks of 64, so it takes 64 clock cycles to initialise the TLB.
The multiple banks of the caches and TLBs are initialised in parallel, so the overall time to initialise the RAMs can very from 64 to 1024 cycles.
The cpu activity may stall for some time after reset, if the cache is required, until the initialisation sequence is completed.
To initialise memory outside of reset, system co-processor (cp15) instructions can be used:
- there is an invalidate all instruction for the I$, in addition to line by line
- D$ can be initialised line by line
- TLB can be invalidated entirely or by individual entry
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